Referring to FIG. 1, a conventional circuit 10 for performing clock and data recovery in a serial data communication device is shown. The circuit 10 requires a reference clock and a clock difference detector. The circuit 10 comprises a half-rate VCO 12, a divider 14, a feedback (FB) divider 15, a frequency difference detector (FDD) 16, a half-rate phase detector (PD) 18, a phase-frequency detector (PFD) 20, a multiplexer 22 and a charge pump filter (CPF) 24. The VCO 12 presents signals from a number of outputs 26a-26n to a number of inputs 27a-27n of the divider 14.
The divider 14 divides the inputs by "M" and presents a clock signal CLOCK-00 and a clock signal CLOCK-90. The clock signal CLOCK-00 is presented to an input 30 of feedback divider 15. The clock signals CLOCK-00 and CLOCK-90 are presented to a number of inputs 32a-32n of the phase detector 18. The divider 15 divides the clock signal CLOCK-00 and presents a divided clock signal DIVIDED at an output 34. The clock signal DIVIDED is presented to an input 36 of the phase-frequency detector 20 and to an input 38 of the frequency difference detector 16.
A reference clock signal REFCLK_IN is presented to an input 40 of the phase-frequency detector 20 and an input 42 of the frequency difference detector 16. The phase-frequency detector 20 compares the signals REFCLK_IN and DIVIDED. A data signal DATA is presented to an input 44 of the phase detector 18. The phase detector 18 has an output 46 that is connected to the multiplexer 22. The phase-frequency detector 20 has an output 48 that is connected to the multiplexer 22. The outputs 46 and 48 present pump-up and pump-down signals.
The multiplexer 22 has an input 50 that receives a control signal LLC. The multiplexer 22 presents a multiplexed signal to an input 52 of the charge pump filter 24 in response to the signal LLC. The frequency difference detector 16 has an output 54 that presents the signal LLC. The frequency difference detector 16 compares the clock signal REFLCK_IN and the clock signal DIVIDED. If the two frequencies are within a certain range, the frequency difference detector 16 toggles the signal LLC. The signal LLC controls the "locking" of the PLL to the clock signal REFCLK_IN or the signal DATA. When the PLL is frequency locked to the clock signal REFCLK_IN, the multiplexer 22 is switched to select the signal DATA. The closed loop of the phase detector 18 then locks to the signal DATA and generates a re-timed data signal RETIMED_DATA and a recovered clock signal RECOVERD_CLK at a number of outputs 56a-56n. The circuit 10 requires the implementation of the reference clock signal REFLCK_IN. Furthermore, the circuit 10 also requires the implementation of the frequency difference detector 16. The circuit 10 implements the half-rate phase detector 18 and a half rate VCO 12.
Referring to FIG. 2, a conventional circuit 60 for performing clock and data recovery in a serial data communication device is shown. FIG. 3 illustrates a timing diagram of the circuit of FIG. 2. The circuit 60 implements an analog phase detector 62 and a digital frequency detector 64. The circuit 60 implements a full-rate clock CLK and corresponding quadrature Q for frequency detection (shown in FIG. 3). The circuit 60 implements dual loop filter design. The output of the phase detector 62 and the output of the frequency detector 64 are added together by the loop filter 66 (i.e., analog summing). The analog phase detector 62 is not robust in the presence of (i) data dependent jitter and/or (ii) missing data transitions. Hence, the circuit 60 provides a low overall jitter tolerance.